An integrated circuit (IC) layout specifies portions of various components of an IC. When the IC is to include a large number of registers, latches, flip-flops and/or other types of clocked devices (“sinks”) that are to be clocked by one or more clocks, the IC must include one or more clock trees for delivering the clock signal from the clock source to all of the sinks to be clocked by it. A clock tree distributes a clock signal from its root to a set of sinks within an IC through a branching network of fan-out buffers. A clock tree includes a hierarchy of fan-out buffers (which may or may not invert the clock signal) for fanning the clock tree out from one or more buffers at a top level of the hierarchy to a large number of buffers at the lowest level of the hierarchy that drive the clock inputs of the sinks.
After establishing positions of all fan-out buffers and routing signal paths between the buffers and the sinks, a clock tree synthesis (CTS) tool estimates the path delays from the clock tree root to all sinks and then inserts additional buffers into various branches of the clock tree as needed to reduce variations in path delays to the sinks, thereby balancing the clock tree. Conventional approaches to positioning fan-out buffers involve grouping sinks into a set of clusters such that each cluster has no more than the number of sinks that can be driven by a single fan-out buffer. Sinks are typically clustered using one of two approaches—a geometry-based approach and a load-based approach.
In an example of the conventional geometry-based approach to clustering, sinks are grouped into clusters such that the clusters have approximately equal spans. With this approach, a portion of the clusters may be sparsely populated with sinks while other clusters may be densely populated with sinks. The geometry-based approach may result in a large number of clusters, which may increase power consumption. Further, the geometry-based approach may be overly time consuming for designs with a large number of sinks.
In an example of the conventional load-based approach to clustering, sinks are grouped into clusters such that the clusters have approximately equal loads (e.g., total pin capacitance). However, this approach frequently results in clusters with large spans that potentially violate slew and skew constraints for the design. Further, the conventional load-based approach fails to account for loading effects of wiring.